Switching circuits having switch elements, such as a DC-to-DC converter, for example, have been employing a higher and higher switching frequency to meet the demand for fast response to load change. Further, a parasitic capacitance of a switch element which drives an inductor has been increased with the increase in output current.
In such a switching circuit, ringing tends to occur at both rising and falling edges where an output current or an output voltage changes. Therefore, a usable switching frequency is limited by the time when the ringing converges, and is thus limited by a parasitic capacitance and a parasitic inductance of wiring or the like.
Generally, a semiconductor chip provided with such a switching circuit is mounted and packaged on a lead frame. The semiconductor chip is mounted in the center of the lead frame regardless of the chip size. Further, there is also known a chip-stacked semiconductor device having multiple semiconductor chips stacked and mounted on a substrate to reduce the substrate area. In the case of a semiconductor device of this type in which first and second semiconductor chips are stacked on the substrate, the first semiconductor chip is disposed with a virtual central axis of the first semiconductor offset from the center of the substrate (for example, refer to JP-A 2005-26564 (Kokai)).
However, the package structure as described above has difficulty in reducing the parasitic inductance and the like, and is limited in increasing the usable switching frequency.